View OP496HRUZ-REEL_4218139.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a operational amplifiers op196/op296/op496 features rail-to-rail input and output swing low power: 60 a/amplifier gain bandwidth product: 450 khz single-supply operation: 3 v to 12 v low offset voltage: 300 v max high open-loop gain: 500 v/mv unity-gain stable no phase reversal applications battery monitoring sensor conditioners portable power supply control portable instrumentation general description the op196 family of cbcmos operational amplifiers features micropower operation and rail-to-rail input and output ranges. the extremely low power requirements and guaranteed opera- tion from 3 v to 12 v make these amplifiers perfectly suited to monitor battery usage and to control battery charging. their dynamic performance, including 26 nv/ hz voltage noise density, recommends them for battery-powered audio applica- tions. capacitive loads to 200 pf are handled without oscillation. the op196/op296/op496 are specified over the industrial (C40 c to +125 c) temperature range. 3 v operation is specified over the 0 c to 125 c temperature range. the single op196 and the dual op296 are available in 8-lead 8-lead narrow-body so 1 2 3 4 8 7 6 5 op196 out a v+ null nc null ?n a +in a v nc = no connect pin configurations 8-lead narrow-body so 1 2 3 4 8 7 6 5 op296 out a in a +in a v out b in b +in b v+ 14-lead narrow-body so 1 2 3 4 5 6 7 14 13 12 11 10 9 8 op496 out d in d +in d v +in c in c out c out a in a +in a v+ +in b in b out b 8-lead tssop op296 out a in a +in a v out b in b +in b v+ 8 1 4 5 14-lead tssop (ru suffix) op496 out a in a +in a v+ out b in b +in b out d in d +in d v out c +in c in c 14 1 7 8 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/ 14 of 14
op196/op296/op496?pecifications electrical specifications parameter symbol conditions min typ max unit input characteristics offset voltage v os op196g, op296g, op496g 35 300 v C40 c t a +125 c 650 v op296h, op496h 800 v C40 c t a +125 c 1.2 mv input bias current i b C40 c t a +125 c 10 50 na input offset current i os 1.5 8na C40 c t a +125 c 20 na input voltage range v cm 05 . 0 v common-mode rejection ratio cmrr 0 v v cm 5.0 v, C40 c t a +125 c6 5 d b large signal voltage gain a vo r l = 100 k ? , 0.30 v v out 4.7 v, C40 c t a +125 c 150 200 v/mv long-term offset voltage v os g grade, note 1 550 v h grade, note 1 1 mv offset voltage drift ? v os / ? t g grade, note 2 1.5 v/ c h grade, note 2 2 v/ c output characteristics output voltage swing high v oh i l = 100 a 4.85 4.92 v i l = 1 ma 4.30 4.56 v i l = 2 ma 4.1 v output voltage swing low v ol i l = C 36 70 mv i l = C1 ma 350 550 mv i l = C2 ma 750 mv output current i out 4ma power supply power supply rejection ratio psrr 2.5 v v s 6 v, C40 c t a +125 c85 db supply current per amplifier i sy v out = 2.5 v, r l = 60 a C40 c t a +125 c4580 a dynamic performance slew rate sr r l = 100 k ? 0.3 v/ s gain bandwidth product gbp 350 khz phase margin ? m 47 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.8 v p-p voltage noise density e n f = 1 khz 26 nv/ hz current noise density i n f = 1 khz 0.19 pa/ hz notes 1 long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5 c, with an ltpd of 1.3. 2 offset voltage drift is the average of the C40 c to +25 c delta and the +25 c to +125 c delta. specifications subject to change without notice. C2C (@ v s = 5.0 v, v cm = 2.5 v, t a = 25 c, unless otherwise noted.) rev. +
electrical specifications parameter symbol conditions min typ max unit input characteristics offset voltage v os op196g, op296g, op496g 35 300 v 0 c t a 125 c 650 v op296h, op496h 800 v 0 c t a 125 c 1.2 mv input bias current i b 10 50 na input offset current i os 1 8na input voltage range v cm 0 3.0 v common-mode rejection ratio cmrr 0 v v cm 3.0 v, 0 c t a 125 c6 0 d b large signal voltage gain a vo r l = 100 k ? 80 200 v/mv long-term offset voltage v os g grade, note 1 550 v h grade, note 1 1 mv offset voltage drift ? v os / ? t g grade, note 2 1.5 v/ c h grade, note 2 2 v/ c output characteristics output voltage swing high v oh i l = 100 a 2.85 v output voltage swing low v ol i l = C100 a70mv power supply supply current per amplifier i sy v out = 1.5 v, r l = 40 60 a 0 c t a 125 c80 a dynamic performance slew rate sr r l = 100 k ? 0.25 v/ s gain bandwidth product gbp 350 khz phase margin ? m 45 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.8 v p-p voltage noise density e n f = 1 khz 26 nv/ hz current noise density i n f = 1 khz 0.19 pa/ hz notes 1 long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5 c, with an ltpd of 1.3. 2 offset voltage drift is the average of the 0 c to 25 c delta and the 25 c to 125 c delta. specifications subject to change without notice. op196/op296/op496 rev. C3C (@ v s = 3.0 v, v cm = 1.5 v, t a = 25 c, unless otherwise noted.) f 1 4
op196/op296/op496 rev. C4C electrical specifications parameter symbol conditions min typ max unit input characteristics offset voltage v os op196g, op296g, op496g 35 300 v 0 c t a 125 c 650 v op296h, op496h 800 v 0 c t a 125 c 1.2 mv input bias current i b C40 c t a +125 c 10 50 na input offset current i os 1 8na C40 c t a +125 c 15 na input voltage range v cm 01 2v common-mode rejection ratio cmrr 0 v v cm 12 v, C40 c t a +125 c6 5 d b large signal voltage gain a vo r l = 100 k ? 300 1000 v/mv long-term offset voltage v os g grade, note 1 550 v h grade, note 1 1 mv offset voltage drift ? v os / ? t g grade, note 2 1.5 v/ c h grade, note 2 2 v/ c output characteristics output voltage swing high v oh i l = 100 a 11.85 v i l = 1 ma 11.30 v output voltage swing low v ol i l = C 70 mv i l = C1 ma 550 mv output current i out 4ma power supply supply current per amplifier i sy v out = 6 v, r l = 60 a C40 c t a +125 c8 0 a supply voltage range v s 31 2v dynamic performance slew rate sr r l = 100 k ? 0.3 v/ s gain bandwidth product gbp 450 khz phase margin ? m 50 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.8 v p-p voltage noise density e n f = 1 khz 26 nv/ hz current noise density i n f = 1 khz 0.19 pa/ hz notes 1 long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5 c, with an ltpd of 1.3. 2 offset voltage drift is the average of the C40 c to +25 c delta and the +25 c to +125 c delta. specifications subject to change without notice. (@ v s = 12.0 v, v cm = 6 v, t a = 25 c, unless otherwise noted.)
op196/op296/op496 rev. C5C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . 15 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite storage temperature range s, ru package . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range op196g, op296g, op496g, h . . . . . . . C40 c to +125 c junction temperature range s, ru package . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . . 300 c package type ja 3 jc unit 8-lead soic 158 43 c/w 8-lead tssop 240 43 c/w 14-lead soic 120 36 c/w 14-lead tssop 180 35 c/w notes 1 absolute maximum ratings apply to 2 for supply voltages less than 15 v, the absolute maximum input voltage is equal to the supply voltage. 3 ja is specified for the worst case conditions caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op196/op296/op496 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
op196/op296/op496 typical performance characteristics rev. C6C input offset voltage v 200 150 100 50 0 250 250 250 200 quantity amplifiers 150 100 50 0 50 100 150 200 v s = 3v t a = 25c count = 400 tpc 1. input offset voltage distribution 200 150 100 50 0 250 250 250 200 quantity amplifiers 150 100 50 0 50 100 150 200 v s = 5v t a = 25c count = 400 input offset voltage v tpc 2. input offset voltage distribution input offset voltage v 200 150 100 50 0 250 250 250 200 quantity amplifiers 150 100 50 0 50 100 150 200 v s = 12v t a = 25c count = 400 tpc 3. input offset voltage distribution input offset drift, tcv os v/ c 20 15 10 5 0 25 4.0 1.0 3.5 quantity amplifiers 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 v s = 5v v cm = 2.5v t a = 40c to 125c tpc 4. input offset voltage distribution (tcv os ) input offset drift, tcv os v/ c 20 15 10 5 0 25 4.0 1.0 3.5 quantity amplifiers 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 v s = 12v v cm = 6v t a = 40c to 125c 1.5 tpc 5. input offset voltage distribution (tcv os ) temperature c input offset voltage v 600 400 400 75 150 50 25 0 25 50 75 100 125 200 0 200 3v v s 12v v cm = v s 2 tpc 6. input offset voltage vs. temperature
op196/op296/op496 rev. C7C temperature c input bais current na 25 20 0 75 150 50 25 0 25 50 75 100 125 15 10 5 v s = 5v v cm = 2.5v tpc 7. input bias current vs. temperature supply voltage v 16 4 212 3 input bias current na 5 12 8 14 tpc 8. input bias current vs. supply voltage common-mode voltage v 40 0 40 2.5 2.5 2.0 input bias current na 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 30 20 20 30 10 10 v s = 2.5v t a = 25c tpc 9. input bias current vs. common-mode voltage load current ma 1000 100 1 0.001 10 0.01 output voltage mv 0.1 1 10 source sink v s = 1.5v tpc 10. output voltage to supply rail vs. load current load current ma 1000 100 1 0.001 10 0.01 output voltage mv 0.1 1 10 source sink v s = 2.5v tpc 11. output voltage to supply rail vs. load current load current ma 1000 100 1 0.001 10 0.01 output voltage mv 0.1 1 10 source sink v s = 6v tpc 12. output voltage to supply rail vs. load current
fre q uency hz 90 80 10 10 1m 100 open-loop gain db 1k 10k 100k 70 60 50 40 30 20 10 0 225 phase shift c 0 45 90 135 180 v s = 2.5v t a = 40c gain phase tpc 16. open-loop gain and phase vs. frequency (no load) fre q uency hz 90 80 10 10 1m 100 open-loop gain db 1k 10k 100k 70 60 50 40 30 20 10 0 225 phase shift c 0 45 90 135 180 v s = 2.5v t a = 125c phase gain tpc 17. open-loop gain and phase vs. frequency (no load) temperature c 950 800 200 75 150 50 open-loop gain v/mv 25 0 25 50 75 100 125 650 500 350 v s = 5v 0.3v < v o < 4.7v r l = 100k tpc 18. open-loop gain vs. temperature temperature c 4.95 4.70 3.7 75 150 50 v oh output voltage v 25 0 25 50 75 100 125 4.45 4.2 3.85 i l = 100a i l = 1ma i l = 2ma v s = 5v tpc 13. output voltage swing vs. temperature temperature c 0.80 0.60 75 150 50 v ol output voltage v 25 0 25 50 75 100 125 0.50 0.30 0.10 i l = 100a i l = 1ma v s = 5v tpc 14. output voltage swing vs. temperature fre q uency hz 90 80 10 10 1m 100 open-loop gain db 1k 10k 100k 70 60 50 40 30 20 10 0 225 phase shift c 0 45 90 135 180 v s = 2.5v t a = 25c phase gain tpc 15. open-loop gain and phase vs. frequency (no load) op196/op296/op496 rev. C8C
op196/op296/op496 rev. C9C load k 500 100 400 300 200 600 0 150 1 100 50 10 2 open-loop gain v/mv v s = 5v t a = 25c tpc 19. open-loop gain vs. resistive load frequency hz 70 60 30 10 1m 100 closed-loop gain db 1k 10k 100k 50 40 30 20 10 0 10 20 v s = 2.5v r l = 10k t a = 25c tpc 20. closed-loop gain vs. frequency fre q uency hz 1000 500 0 100 1m 1k output impedance 10k 100k 900 800 700 600 400 300 200 100 a cl = 10 a cl = 1 v s = 2.5v t a = 25c tpc 21. output impedance vs. frequency fre q uency hz cmrr db 140 40 100 10m 1k 10k 100k 1m 120 100 80 60 40 20 0 20 v s = 2.5v t a = 25 c all channels 160 tpc 22. cmrr vs. frequency psrr db fre q uency hz 160 140 40 10 10m 100 1k 10k 1m 100k 120 100 80 60 40 20 0 20 v s = 5v t a = 25 c +psrr psrr tpc 23. psrr vs. frequency frequency hz 6 5 0 1k 1m 10k maximum output swing v 100k 4 2 3 1 v s = 2.5v v in = 5v p-p a v = 1 r l = 100k tpc 24. maximum output swing vs. frequency
temperature c 90 50 20 75 150 50 i sy /amplifier a 40 25 0 25 50 8575 100 125 80 70 40 30 60 v s = 12v v s = 3v v s = 5v tpc 25. supply current/amplifier vs. temperature supply voltage v 55 50 35 113 3 i sy /amplifier a 5791112 45 40 t a = 25 c tpc 26. supply current/amplifier vs. supply voltage frequency hz 80 70 0 11 k 10 100 60 50 40 30 20 10 voltage noise density nv/ hz v s = 2.5v t a = 25c v cm = 0v tpc 27. voltage noise density vs. frequency frequency hz 0.6 0.5 0 11k 10 current noise density pa/ hz 100 0.4 0.3 0.2 0.1 v s = 2.5v t a = 25c v cm = 0v tpc 28. input bias current noise density vs. frequency settling time s 10 10 03 0 5 input step v 10 15 20 25 8 2 4 6 8 6 4 0 2 output swing output swing v s = 6v t a = 25c to 0.1% tpc 29. settling time to 0.1% vs. step size 10 0% 100 90 1s 2mv v s = 2.5v a v = 10k e n = 0.8 v p-p tpc 30. 0.1 hz to 10 hz noise op196/op296/op496 rev. C10C
op196/op296/op496 rev. C11C 1x 1x 2x 2x q8 q7 q6 q5 r4a r4b i2 1x 1x q4 q3 2x 2x q2 q1 r3a r3b q9 i3 q13 q11 d3 q12 qc1 q10 qc2 q15 cc1 q14 r2 r1 i1 r6 cf1 d4 q17 d5 q18 r5 r7 ql1 q16 cf2 d6 q19 2x 1x i4 cc2 d7 1 * 5 * q20 1.5x 1x d10 r9 d8 q21 r8 d9 q22 q23 i5 out +in in v ee v cc * op196 only tpc 36. simplified schematic 10 0% 100 90 2 s 20mv v s = 2.5v a v = 1 r l = 10k c l = 100pf t a = 25c 100mv 0v tpc 31. small signal transient response 10 0% 100 90 v s = 2.5v a v = 1 r l = 100k c l = 100pf t a = 25c 2 s 20mv 100mv 0v tpc 32. small signal transient response 10 0% 100 90 1v v s = 2.5v r l = 10k 10 s tpc 33. large signal transient response 10 0% 100 90 1v v s = 2.5v r l = 100k 10 s tpc 34. large signal transient response ch a: 40.0v fs 5.00v/div mkr: 36.8v/ hz 0hz 10hz mkr: 1.00hz bw: 145mhz tpc 35. 1/f noise corner, v s = 5 v, a v = 1,000
op196/op296/op496 rev. C12C applications information functional description the op196 family of operational amplifiers is comprised of single- supply, micropower, rail-to-rail input and output amplifiers. input offset voltage (v os ) is only 300 v maximum, while the output will deliver 5 ma to a load. supply current is only 50 a, while bandwidth is over 450 khz and slew rate is 0.3 v/ s. tpc 36 is a simplified schematic of the op196it displays the novel cir- cuit design techniques used to achieve this performance. input overvoltage protection the opx96 family of op amps uses a composite pnp/npn input stage. transistor q1 in figure 36 has a collector-base voltage of 0 v if +in = v ee . if +in then exceeds v ee , the junc- tion will be forward biased and large diode currents will flow, which may damage the device. the same situation applies to +in on the base of transistor q5 being driven above v cc . there- fore, the inverting and noninverting inputs must not be driven above or below either supply rail unless the input current is limited. figure 1 shows the input characteristics for the opx96 family. this photograph was generated with the power supply pins connected to ground and a curve tracers collector output drive connected to the input. as shown in the figure, when the input voltage exceeds either supply by more than 0.6 v, internal pn-junctions energize and permit current flow from the inputs to the supplies. if the current is not limited, the amplifier may be damaged. to prevent damage, the input current should be limited to no more than 5 ma. 10 0% 100 90 8 6 4 2 0 2 4 6 8 1.5 1 0.5 0 0.5 1 1.5 input voltage v input current ma figure 1. input overvoltage i-v characteristics of the opx96 family output phase reversal some other operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. typically for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. with these common-mode limited devices, external clamping diodes are required to prevent input signal excursions from exceeding the devices negative supply rail (i.e., gnd) and triggering output phase reversal. the opx96 family of op amps is free from output phase reversal effects due to its novel input structure. figure 2 illustrates the performance of the opx96 op amps when the input is driven beyond the supply rails. as previously mentioned, amplifier input current must be limited if the inputs are driven beyond the supply r ails. in the circuit of figure 2, the source ampli- tude is 15 v, while the supply voltage is only 5 v. in this case, a 2 k ? source resistor limits the input current to 5 ma. 10 0% 100 90 v s = 5v a v = 1 5v 1ms 5v 0 0 v in v out voltage 5v/div time 1ns/div figure 2. output voltage phase reversal behavior input offset voltage nulling the op196 provides two offset adjust terminals that can be used to null the amplifiers internal v os . in general, operational amplifier terminals should never be used to adjust system offset voltages. a 100 k ? potentiometer, connected as shown in fig- ure 3, is recommended to null the op196s offset voltage. offset nulling does not adversely affect tcv os performance, providing that the trimming potentiometer temperature coefficient does not exceed 100 ppm/ c. 6 7 2 3 v v+ op196 100k 4 1 5 figure 3. offset nulling circuit driving capacitive loads op196 family amplifiers are unconditionally stable with capaci- tive loads less than 170 pf. when driving large capacitive loads in unity-gain configurations, an in-the-loop compensation technique is recommended, as illustrated in figure 4. op296 c f v in r g r f r x c l v out r x = where r o = open-loop output resistance r o r g r f c f = i + ( ) ( ) c l r o i | a cl | r f + r g r f figure 4. in-the-loop compensation technique for driving capacitive loads
op196/op296/op496 rev. C13C a micropower false-ground generator some single supply circuits work best when inputs are biased above ground, typically at 1/2 of the supply voltage. in these cases, a false-ground can be created by using a voltage divider buffered by an amplifier. one such circuit is shown in figure 5. this circuit will generate a false-ground reference at 1/2 of the supply voltage, while drawing only about 55 a from a 5 v supply. the circuit includes compensation to allow for a 1 f bypass capacitor at the false-ground output. the benefit of a large capacitor is that not only does the false-ground present a very low dc resistance to the load, but its ac impedance is low as well. 6 2 3 10k op196 100 4 5v or 12v 0.022f 1f 240k 240k 1f 2.5v or 6v 7 figure 5. a micropower false-ground generator single-supply half-wave and full-wave rectifiers an op296, configured as a voltage follower operating from a single supply, can be used as a simple half-wave rectifier in low frequency (<400 hz) applications. a full-wave rectifier can be configured with a pair of op296s as illustrated in figure 6. a1 8 1 3 4 5v 1/2 op296 2k 2 a2 5 6 2vp-p < 500hz 7 1/2 op296 r1 100k r2 100k v out a full-wave rectified output v out b half-wave rectified output 10 0% 100 90 500mv 1v 500s 500mv f = 500hz input v out b (half-wave output) v out a (full-wave output) figure 6. single-supply half-wave and full-wave rectifiers using an op296 the circuit works as follows: when the input signal is above 0 v, the output of amplifier a1 follows the input signal. since the noninverting input of amplifier a2 is connected to a1s output, op amp loop control forces a2s inverting input to the same potential. the result is that both terminals of r1 are at the same potential and no current flows in r1. since there is no current flow in r1, the same condition must exist in r2; thus, the output of the circuit tracks the input signal. when the input signal is below 0 v, the output voltage of a1 is forced to 0 v. this condition now forces a2 to operate as an inverting voltage follower because the noninverting terminal of a2 is also at 0 v. the output voltage of v out a is then a full-wave rectified vers ion of the input signal. a resistor in series with a1s noninverting input protects the esd diodes when the input signal goes below ground. square wave oscillator the oscillator circuit in figure 7 demonstrates how a rail-to-rail output swing can reduce the effects of power supply variations on the oscillators frequency. this feature is especially valuable in battery powered applications, where voltage regulation may not be available. the output frequency remains stable as the supply voltage changes because the rc charging current, which is derived from the rail-to-rail output, is proportional to the supply voltage. since the schmitt trigger threshold level is also proportional to supply voltage, the frequency remains relatively independent of supply voltage. for a supply voltage change from 9 v to 5 v, the output frequency only changes about 4 hz. the slew rate of the amplifier limits the oscillation frequency to a maximum of about 200 hz at a supply voltage of 5 v. 59k 1/2 op296/ op496 100k 100k freq out f osc = < 200hz @ v+ = 5v 1 rc c v+ r 2 3 4 8 1 figure 7. square wave oscillator has stable frequency regardless of supply voltage changes a 3 v low dropout, linear voltage regulator figure 8 shows a simple 3 v voltage regulator design. the regu- lator can deliver 50 ma load current while allowing a 0.2 v dropout voltage. the op296s rail-to-rail output swing easily drives the mje350 pass transistor without requiring special drive circuitry. with no load, its output can swing to less than the pass transistors base-emitter voltage, turning the device nearly off. at full load, and at low emitter-collector voltages, the transistor beta tends to decrease. the additional base current is easily handled by the op296 output. the ad589 provides a 1.235 v reference voltage for the regula- tor. the op296, operating with a noninverting gain of 2.43, drives the base of the mje350 to produce an output voltage of 3.0 v. since the mje350 operates in an inverting (common- emitter) mode, the output feedback is applied to the op296s noninverting input.
op196/op296/op496 rev. C14C 1/2 op296 4 1 3 2 8 1000pf 44.2k 1% 30.9k 1% ad589 43k 1.235v mje 350 100f v in 5v to 3.2v i l < 50ma v o figure 8. 3 v low dropout voltage regulator figure 9 shows the regulators recovery characteristics when its output underwent a 20 ma to 50 ma step current change. 10 0% 100 90 2v 50s 10mv 50ma 30ma output step current control waveform figure 9. output step load current recovery buffering a dac output multichannel trimdacs ? such as the ad8801/ad8803, are widely used for digital nulling and similar applications. these dacs have rail-to-rail output swings, with a nominal output resistance of 5 k ? . if a lower output impedance is required, an op296 amplifier can be added. two examples are shown in figure 10. one amplifier of an op296 is used as a simple buffer to reduce the output resistance of dac a. the op296 provides rail-to-rail output drive while operating down to a 3 v supply and requiring only 50 a of supply current. 5v op296 simple buffer 0v to 5v +4.983v +1.1mv r1 100k summer circuit with fine trim adjustment digital interfacing omitted for clarity ad8801/ ad8803 v h v l v dd v refh gnd v refl v h v l v h v l figure 10. buffering a trimdac outputtpc the next two dacs, b and c, sum their outputs into the other op296 amplifier. in this circuit dac c provides the coarse output voltage setting and dac b is used for fine adjustment. the insertion of r1 in series with dac b attenuates its contri- bution to the voltage sum node at the dac c output. a high-side current monitor in the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistors long-term reliability over a wide range of load current conditions. as a result, monitoring and limiting device power dissipation is of prime importance in these designs. the circuit illustrated in figure 11 is an example of a 5 v, single-supply high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. this design uses an op296s rail-to- rail input voltage range to sense the voltage drop across a 0.1 ? current shunt. a p-channel mosfet is used as the feedback element in the circuit to convert the op amps differential input voltage into a current. this current is then applied to r2 to gen- erate a voltage that is a linear representation of the load current. the transfer equation for the current monitor is given by: monitor output = r 2 r sense r 1 ? ? ? ? ? ? i l for the element values shown, the monitor outputs transfer characteristic is 2.5 v/a. 8 1 2 3 4 1/2 op296 5v 5v s g d m1 3n163 monitor output r2 2.49k r1 100 r sense 0.1 i l 5v figure 11. a high-side load current monitor a single-supply rtd amplifier the circuit in figure 12 uses three op amps on the op496 to produce a bridge driver for an rtd amplifier while operating from a single 5 v supply. the circuit takes advantage of the op496s wide output swing to generate a bridge excitation voltage of 3.9 v. an ad589 pr ovides a 1.235 v reference for the bridge current. op amp a1 drives the bridge to maintain 1.235 v across the parallel combination of the 6.19 k ? and 2.55 m ? resistors, which generates a 200 a current source. this current divides evenly and flows through both halves of the bridge. thus, 100 a flows through the rtd to generate an output voltage which is proportional to its resistance. for improved accuracy, a 3-wire rtd is recommended to balance the line resistance in both 100 ? legs of the bridge. trimdac is a registered trademark of analog devices inc.
op196/op296/op496 rev. C15C * op496 spice macro-model rev. c, 5/95 * arg / adsc * * copyright 1995 by analog devices, inc. * * refer to readme.doc file for license statement. * use of this model indicates your acceptance of the * terms and provisions in the license statement. * * node assignments * noninverting input * inverting input * positive supply * negative supply * output * * .subckt op496 1 2 99 50 49 * * input stage * iref 21 50 1u qb1 21 21 99 99 qp 1 qb2 22 21 99 99 qp 1 qb34 219999qp1.5 qb4 22 22 50 50 qn 2 qb5 11 22 50 50 qn 3 q154750qn2 q264850qn2 q344750qn1 q444850qn1 q5501799qp2 q6503899qp2 eos 3 2 poly(1) (17,98) 35u 1 q7991950qn2 q8993 1050qn2 q9 12 11 9 99 qp 2 q10 13 11 10 99 qp 2 q11 11 11 9 99 qp 1 q12 11 11 10 99 qp 1 r1 99 5 50k r2 99 6 50k r3 12 50 50k r4 13 50 50k ios 1 2 0.75n c10 5 6 3.183p c11 12 13 3.183p cin 1 2 1p * * gain stage * eref 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5 g1 98 15 poly(2) (6,5) (13,12) 0 10u 10u r10 15 98 251.641meg cc 15 49 8p d1 15 99 dx d2 50 15 dx * * common-mode stage * ecm 16 98 poly(2) (1,98) (2,98) 0 0.5 0.5 r11 16 17 1meg r12 17 98 10 * * output stage * isy 99 50 20u ein 35 50 poly(1) (15,98) 1.42735 1 q24 37 35 36 50 qn 1 qd4 37 37 38 99 qp 1 q27 40 37 38 99 qp 1 r5 36 39 150k r6 99 38 45k q26 39 42 50 50 qn 3 qd5 40 40 39 50 qn 1 q28 41 40 44 50 qn 1 ql1 37 41 99 99 qp 1 r7 99 41 10.7k i4 99 43 2u qd7 42 42 50 50 qn 2 qd6 43 43 42 50 qn 2 q29 47 43 44 50 qn 1 q30 44 45 50 50 qn 1.5 qd10 45 46 50 50 qn 1 r9 45 46 175 q31 46 47 48 99 qp 1 qd8 47 47 48 99 qp 1 qd9 48 48 51 99 qp 5 r8 99 51 2.9k i5 99 46 1u q32 49 48 99 99 qp 10 q33 49 44 50 50 qn 4 .model dx d() .model qn npn(bf=120vaf=100) .model qp pnp(bf=80 vaf=60) .ends v out 5v a3 a2 a1 100k 0.1f 1/4 op496 1/4 op496 100k gain = 259 200 10-turns 26.7k 26.7k 100 6.17k 37.4k 5v 100 rtd 2.55m ad589 1/4 op496 note: all resistors 1% or better 392 392 20k figure 12. a single-supply rtd amplifier amplifiers a2 and a3 are configured in a two op amp instru- mentation amplifier configuration. for ease of measurement, the ia resistors are chosen to produce a gain of 259, so that each 1 c increase in temperature results in a 10 mv increase in the output voltage. to reduce measurement noise, the band- width of the amplifier is limited. a 0.1 f capacitor, connected in parallel w ith the 100 k ? resistor on amplifier a3, creates a pole at 16 hz.
op196/op296/op496 C18C rev. e outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure13. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 14. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches)
op196/op296/op496 rev. e C17C 8 5 4 1 pin 1 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 0.20 0.09 8 0 6.40 bsc 4.50 4.40 4.30 3.10 3.00 2.90 coplanarit y 0.10 0.75 0.60 0.45 compliant to jedec standards mo-153-aa figure 15. 8-lead thin shrink small outline package [tssop] (ru-8) dimensions shown in millimeters compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 16. 14-lead thin shrink small outline package (ru-14) dimensions shown in millimeters
op196/op296/op496 C18C rev. e ordering guide model 1, 2 temperature range package description package option op196gsz ?40c to +85c (ambient) 8-lead soic_n r-8 op196gsz-reel ?40c to +85c (ambient) 8-lead soic_n r-8 op196gsz-reel7 ?40c to +85c (ambient) 8-lead soic_n r-8 op296gsz ?40c to +85c (ambient) 8-lead soic_n r-8 op296gsz-reel ?40c to +85c (ambient) 8-lead soic_n r-8 op296gsz-reel7 ?40c to +85c (ambient) 8-lead soic_n r-8 op296hruz-reel ?40c to +85c (ambient) 8-lead tssop ru-8 op496gs ?40c to +85c (ambient) 14-lead soic_n r-14 op496gs-reel ?40c to +85c (ambient) 14-lead soic_n r-14 op496gs-reel7 ?40c to +85c (ambient) 14-lead soic_n r-14 op496gsz ?40c to +85c (ambient) 14-lead soic_n r-14 op496gsz-reel ?40c to +85c (ambient) 14-lead soic_n r-14 op496gsz-reel7 ?40c to +85c (ambient) 14-lead soic_n r-14 OP496HRUZ-REEL ?40c to +85c (ambient) 14-lead tssop ru-14 1 z = rohs compliant part. 2 note op496gs, op496gs-reel, and op496gs- reel7 are not rohs compliant parts.
op196/op296/op496 rev. e C19C revision history 9/11rev. d to rev. e changes to general description section ....................................... 1 changes to electrical specifications table (@v s = 5.0 v), output voltage swing high and output swing low parameters, conditions column .......................................................................... 2 change to electrical specifications table (@v s = 12.0 v), output swing low parameter, conditions column .................... 4 changes to ordering guide ........................................................... 18 12/10rev. c to rev. d change to data sheet title .............................................................. 1 deleted dip pin configuration figures ......................................... 1 changes to absolute maximum ratings table and package type table, moved ordering guide ............................................... 5 updated outline dimensions ........................................................ 16 changes to ordering guide ........................................................... 16 1/02rev. b to rev. c edits to typical performance characteristics ............................. 10 ?2002C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00312-0-9/11(e)

▲Up To Search▲

Price & Availability of OP496HRUZ-REEL

	To Download OP496HRUZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .